Current generating circuits are well known in the art and in their simplest form consist of a pair of matched current mirror transistors, each having a controllable path and a control node for controlling conduction of the controllable path. In bipolar technology, the control node is the base and the controllable path is from collector to emitter. In MOS technology, the control node is the gate and the controllable path is the source/drain channel. The present invention is concerned particularly but not exclusively with bipolar technology. One of the transistors has a current setting resistor connected in its controllable path and has its control node connected to the control node of one transistor and also into its own controllable path. When a current flows through the current setting resistor, the same current is caused to flow in the controllable path of the other transistor and can be used to drive a suitable output transistor to generate a source reference current related to that current through the area ratio of the output transistor and the current mirror transistors. Another pair of matched current mirror transistors is connected in series with the first pair between a supply voltage and ground and drives an output transistor to generate a sink reference current. In practical terms, the basic current mirror circuit has many limitations. One of these is that its impedance is too low for it to act as a perfect current source or sink when connected to other circuitry. To increase the impedance, it is common to include a pair of matched cascode transistors connected respectively to each current mirror transistor for each of source and sink current generating parts.
FIGS. 1A and 1B illustrate a source/sink current generating circuit of this type. The circuit comprises a first current mirror circuit for generating a source current and a second current mirror circuit for generating a sink current. The first current mirror circuit comprises a first set of matched p-n-p bipolar transistors Q1,Q2. These transistors have their emitters connected to a supply voltage Vdd and their bases connected to each other. In conventional current mirror fashion, the base of the second transistor Q2 is connected to its collector. A second set of similarly connected transistors Q3,Q4 is connected in cascode to the first set. A second current mirror circuit comprises a third set of matched n-p-n transistors Q5,Q6 connected in current mirror fashion. The collectors of these transistors Q5,Q6 are connected to the emitters of the transistors Q3,Q4 respectively. The second current mirror circuit also comprises a fourth set of transistors Q7,Q8 connected in cascode with the third set Q5,Q6. There is a set of output transistors Q9,Q10 connected to the first current mirror circuit and a set of output transistors Q11,Q12 connected to the second current mirror circuit. As is known, the collector current Isource through the output transistors Q9,Q10 is related to the collector current through the transistors Q2 and Q4. Likewise, the current Isink through the output transistors Q11,Q12 is related to the collector current through the transistors Q6,Q8. This collector current is set by a current setting resistor R connected to the emitter of the transistor Q8. The sink and source currents Isink, Isource are thus both related to the collector current set by the resistor R. Thus, provided that the sizes of the current mirror transistors in the first and second current mirror circuits are substantially the same, the sink and source currents are substantially matched.
However, the circuit of FIGS. 1A and 1B unsatisfactory in some circumstances. In particular, if a particular manufacturing process has significant process variations affecting the transistors, the currents Isink and Isource will no longer be properly matched. This is due in part to the fact that process variations will affect p-n-p type transistors in a manner differently to n-p-n transistors, thus affecting the current sink generating part of the circuit in a manner differently from the current source generating part of the circuit. One object of the present invention is to provide a current generating circuit in which the source and sink currents remain substantially matched despite process variations.
A common use of a current generating circuit of the type illustrated in FIGS. 1A and 1B to provide several current sinks and/or sources. To do this, separate sets of transistors corresponding to Q9,Q10 for the current source and Q11,Q12 for the current sink are connected in parallel to provide separate current generating arrangements. Taking the current sink generating part of the circuit as an example, consider n sets of transistors connected in parallel with Q11,Q12, each having the same size as Q11,Q12. The base current required to drive the output transistors is nIb where Ib is the base current supplied to the base of each of the transistors Q11,Q12. This base current is derived from the collector current of Q5 and Q8 respectively. For a single set of output transistors, the assumption is made that the base current is very small compared to the collector current and so does not significantly affect the operation of the current mirror circuits. However, if a significant number of extra sets of transistors are connected to supply a plurality of current sinks, the amount of base current required to be supplied increases to such an extent that it does affect the collector currents in the current mirror circuits and thus the reference current and also affects the matching of the sink and source currents. The ability to drive these sets of transistors without the reference current being adversely affected is called the fan-out capability of the circuit.
FIGS. 1A and 1B illustrate the magnitude of the currents flowing in each branch of the circuit, where n is the number of sets of output transistors, Ibp is the base current for a p-type transistor and Ibn is the base current for an n-type transistor. Thus EQU Isource=n [I-(2n+5)Ibp+nIbn] EQU Isink=n [I-(2n+5)Ibp-2Ibn]
Hence the mismatch current Imismatch=Isource-Isink=n[nIbn+2Ibn]=n(n+2)Ibn
and thus depends on both n and Ibn. With the circuit of FIGS. 1A and 1B therefore, there will always be a mismatch current, and this will increase as n increases.
The present invention seeks to provide a circuit which overcomes these problems. Further, the present invention seeks to provide a circuit which has a high DC power supply rejection ratio and can operate with a low supply voltage (down to 1.4 V).